The present invention relates to a memory device. More particularly, the present invention relates to a semiconductor device having a coaxial type gate structure and a method for fabricating the same.
When the channel length of a cell transistor is decreased, the ion concentration of the cell channel structure is generally increased in order to maintain threshold voltage of the cell transistor. Due to the increase in the ion concentration of the cell channel structure, an electric field in the source/drain regions of the cell transistor is enhanced to increase leakage current. This results in the degradation of the refresh characteristics of a DRAM structure. In addition, as the semiconductor device shrinks to smaller sizes, it is difficult to solve problems regarding the short channel effect (“SCE”). Therefore, new structures of the transistor such as a recess gate transistor and a fin channel transistor have been proposed to increase the channel length of the cell transistor.
However, these structures of the semiconductor device can not completely surround the channel structure of the transistor, which causes problems in gate controllability and the performance of the device. Accordingly, there is a need for a new structure of the transistor in order to improve the gate controllability and performance of the device.